Using 0.18μm and below technologies at high-performance VLSI chips is facing many challenges. Such as interconnect line effect by feature size shrink ,the impact of timing from the signal integrity, and the timing complicated because the interdependence of many design variable. So designers have to be deeply involved in physical design, use effective EDA tools, and have to develop the back-end design flow. This paper introduces the back-end physical design process of an ASIC based on a tool named Soc Encounter of Cadence ,and the layout is displayed and taped out in SMIC 0.18μm CMOS process. This design is divided into data preparation,floorplan,cell placement,clock tree synthesis,routing and so on. Considering the interconnect effect of the deep sub-micron process, this paper describes how to prevent crosstalk, and how to ensure the chip timing to meet the design requirement through the whole back-end design.% 采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战，如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂，使芯片版图设计师需深入介入物理设计，选用有效的EDA工具，结合电路特点开发有针对性的后端设计流程.文章介绍了采用Cadence公司Soc Encounter后端工具对基于0.18μm工艺的ASIC芯片后端设计过程，分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍.同时考虑到深亚微米工艺下的互联线效应，介绍了如何预防串扰问题，以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求.
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