分离栅式快闪存储器抗编程干扰性能的工艺优化

摘要

随着电子产品的普及，分离栅式快闪存储器作为闪存的一种，因其具有高效的编程速度以及能够完全避免过擦除的能力，无论是在单体还是嵌入式产品方面都得到了人们更多的关注。但由于快闪存储器产品规则的阵列排列方式，高速的编程能力也带来了容易出现编程干扰的问题，成为了制约其实际应用的关键因素。从工艺优化方面探讨在编程过程中，如何有效提高分离栅式快闪存储器的抗编程干扰性能。通过实验发现通过整合改进工艺流程中调节字线阈值电压的离子注入方式的方法，可以显著改进分离栅式工艺快闪存储器的抗编程干扰性能。%As of the popularity of various electronic products, the split-gate flash, one kind of the flash memories, due to its highly efficient programming speed and the ability to completely avoid over-erase issue, got more and more attention both in stand-alone and embedded applications. But with highly efifcient programming speed in the regular cell array, the program disturb has been the bottleneck of the application of such split-gate lfash. The paper studied on how to improve anti-program performance through process optimization. With the optimized integration scheme on the threshold voltage adjustment implantation of word line, the anti-program disturb performance of such kind of split-gate lfash can be greatly improved.