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Non volatile memory array with split gate cells and method for avoiding disturbance when programming
Non volatile memory array with split gate cells and method for avoiding disturbance when programming
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机译:具有分离栅单元的非易失性存储器阵列以及在编程时避免干扰的方法
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摘要
The circuit has a table including non volatile memory cells (24A-24D), and a control logic delivering a programming voltage (VPROG) to a control gate of the cell (24A) to be programmed, through a word control line (18). A blocking logic delivers a blocking voltage (VBLOCK1) higher than the programming voltage, to the cell (24B) sharing the same line (18), through a bit control line (22) corresponding to the cell (24B). An independent claim is also included for a method of programming a memory cell of a table of an integrated circuit.
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