应用于通信系统中的高性能Viterbi译码器实现

摘要

We propose a high-speed Viterbi decoder imlementations based on ASIC. In order to cope with a wireless communication system for hign frequency and throughput requirement. The Viterbi decoder plus a fully parallel structure comparison module in the case of less constraint of 9. Performance analysis results show that rtl code for logic synthesis by using thssynopsys design compiler. Finally obtainted area is 0.2 mm2, power consumption is 18 mW, throughtput sent to 82 Mbps under clock frequency of 166 MHz.%针对无线通信系统中对于高频率、高吞吐量的要求，提出了一种基于ASIC的高速Viterbi译码器实现方案。该译码器在约束度小于等于9的情况下，采用全并行结构的加比选模块。性能分析结果表明，在SMIC 40 nm工艺，通过使用Synopsys Design Compiler对RTL 代码进行逻辑综合，该译码器在时钟频率为166 MHz情况下，最终得到面积为0．2 mm2，功耗为18 mW，吞吐量达到82 Mbps。