DSP与FPGA异步数据传输方法

摘要

国内GPS卫星信号模拟源大多基于“DSP+FPGA”架构进行开发研制,DSP与FPGA是两个独立的时钟域系统,存在异步数据交互的问题.基于解决DSP计算所得导航电文以及载波控制字、伪码控制字向FPGA传输时发生数据丢失问题得目的,提出采用异步FIFO来缓存大量导航电文数据还有同步器来同步所传输的载波控制字和伪码控制字的方法.通过采用Altera公司的FIFO内核来进行外围接口信号和控制逻辑设计以及两级触发器级联来实现同步器的试验设计方法,得到所设计的缓存导航电文的异步FIFO输出的数据结果正确以及系统稳定的结论.%Domestic GPS simulators are mostly developed based on the "DSP+FPGA" framework.FPGA and DSP are two independent clock domain system whichhasa problem of asynchronous data exchange.In order to solve the problem of missing data which happens between DSP and FPGA when the navigation message and carrier control words,pseudo code control wordsare tramissed.It is proposed that using asyn-chronous FIFO to cache a large number of navigation message data and using a synchronizer to synchronize the transmission carrier control words and pseudo code control words.This design is based on the FIFO core of Altera company.It is used todesign the peripheral interface signal and the control logic.The synchronization device is realized through the cascade of the two stage trigger.Experimental results show that the data is not lost and the system is stable based on the proposed method.