基于Muller_C单元和DICE单元的抗辐照D触发器设计

摘要

Currently, smaller feature sizes and higher frequencies of deep sub-micron integrated circuits make Ics susceptible to single-event upset (SEU) and single-event transient(SET). In this paper, two kinds of timing sampling latches based on the static circuit and dynamic circuits of Muller_C are designed. Meanwhile, combining with the DICE latch, two D flip-flops which can tolerate both of SEU and SET are also designed. Based on the 3D TCAD Mixed mode simulation SET is created and injected into the circuit netlist which obtain the RC parasitic parameters from the layout. The Hspice simulation results show that, these two DFFs can tolerate SEU and SET efficiently. Compared with the SEU and SET tolerant DFFs in [1], these two presented DFFs need less area, dynamic power, and static power at the frequency of 500 MHz, and one of the DFFs has a shorter setup time.%随着工艺尺寸的缩减,单粒子翻转(SEU)和单粒子瞬态(SET)成为了深亚微米集成电路中备受关注的可靠性问题.本文基于Muller_C单元的静态电路和动态电路,设计了两种时域采样锁存器,并与DICE锁存器相结合,设计出了相应的既抗SEU又抗SET的D触发器(D flip-flops,简称DFF).通过三维TCAD混合模拟产生的SET,对两种D触发器版图后提取寄生参数的电路网表进行故障注入模拟,Hspice模拟的结果证明:两种DFF在有效抑制SEU的同时,还可以有效地抑制SET.与文献[1]中提出的既抗SEU又抗SET的DFF相比,本文中设计的DFF面积较小,500MHz下动态功耗和静态功耗均有所降低,其中一个DFF的建立时间优于文献[1]中的DFF.