一款面向高性能SOC应用的高精度全数字锁相环设计

摘要

锁相环(PLL)是高性能SOC中必不可少的器件,为芯片提供系统时钟.提出了一款面向高性能SOC应用的高精度全数字锁相环结构,并采用了全新的高精度时间数字转换器(TDC)结构提高鉴相精度,降低TDC的相位噪声,改善了锁相环抖动性能.在先进工艺下完全采用数字标准单元实现了此全数字锁相环系统,解决了模拟电路中无源器件面积过大、抗噪声能力不强以及工艺移植性差等瓶颈问题.该系统最高频率可达到2.6 GHz,抖动性能小于2 ps.%Phase Locked Loop (PLL) is an essential part of high-performance SOCs that provide the chip with a system clock.This paper presents a novel All-Digital Phase-Locked Loop (ADPLL) structure for high-performance SOC applications and a novel high-resolution Time-to-Digital Converter (TDC) improves the phase detection precision and reduces the TDC phase noise and improves the PLL jitter performance.In the nanometer process,the ADPLL system is implemented by using digital standard cells,which solves the bottleneck problems such as poor portability to new process,big area of passive devices,and poor anti-noise ability in analog circuits.The system has the maximum frequency of 2.6GHz and the jitter performance less than 2 picoseconds.