FDTD算法的FPGA实现

摘要

Finite Difference Time Domain (FDTD) is a very important method for the numerical simulation of electro-magnetic waves,but the method is more computational time demanding for electrical-large size problems. In order to reduce the computation time,an FPGA hardware circuit to accomplish FDTD computation is designed. Pipeline,par-allelism and dual-port RAM are used to improve the hardware performance. The simulation results show that the FPGA implementation speeds up the algorithm greatly.%FDTD是电磁波数值仿真的重要方法,应用中的主要问题是对于大尺寸仿真,计算量太大.为了提高计算速度,采用FPGA来实现FDTD算法,通过设计专门的硬件计算电路,来提高计算速度.在设计中采用了流水线技术、并行计算等方法加速措施,并采用双口RAM存储数据,极大地减少了数据读取时间.综合以上方法可以使算法的运算速度得到明显的提升.