基于RapidIO的FPGA硬件抽象层设计

摘要

According to the specifications of MHAL in the system of software communications architecture version 2.2.2(SCA2.2.2), this paper proposes s a MHAL design method based on FPGA with RapidIO IP core, which separates the FPGA waveform design from the specific hardware platform. High reliability and low latency RapidIO bus is used for hardware platform interconnection. The function and performance has been verified through simulation software and hardware platform. There is a great reference value for practical application.%本文针对 SCA2.2.2软件通信体系结构提出的硬件抽象层（MHAL）设计规范，研究设计了一种现场可编程逻辑门阵列（FPGA）上基于RapidIO总线IP核的MHAL，实现了波形设计与具体硬件平台分离。该设计基于采用适合嵌入式通信系统的高速可靠、低延迟的 RapidIO 总线联接的硬件平台。通过仿真软件和硬件平台对其功能和性能进行了验证，对实际工程应用有极大的参考价值。