The increasing variations in manufacturing process parameters with technology scaling has led to the adoption of statistical design methodologies in favor of the existing static or worst-case approaches. However, statistical circuit, analysis and optimization techniques have primarily been embraced at the lower levels of design abstraction, while system-level designers continue to use the conventional static approaches. This thesis demonstrates that modeling and mitigating the impact of process variations at the system-level is indeed possible and, more importantly, beneficial. Towards this end, we make four specific contributions: (1) Mitigating the performance lost by fully-synchronous systems to process variations using a multiple clock domain (MCD) design style. An efficient algorithm to compute the distribution of throughput of an MCD system is proposed and provides significant speed-up compared to Monte Carlo simulations. (2) Mitigating the impact of process variations on the leakage power dissipation of hilly-synchronous systems using system-level body-bias island partitioning. An efficient algorithm is proposed to compute the optimal body-bias island partitioning, and provides significant, speed-up compared to a competing approach while providing similar reduction ill the mean and variance of leakage power. (3) 3D-GCP, a system-level model for analyzing the impact of process variations on the frequency of fully-synchronous 3D ICs. The accuracy of the 3D-GCP model is verified against detailed SPICE based circuit simulations. (4) Mitigating the impact of process variations on the performance of fully-synchronous 3D ICs using a novel variability-aware 3D integration scheme. The proposed scheme significantly increases the number of assembled 3D systems that meet a specified performance constraint, as compared to conventional 3D integration.
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