We are at the beginning of the billion-transistor era of application specific chips. The design of such chips for numerous applications, like military, communications, etc., faces demanding challenges due to huge complexity of systems, from one side, and increasing design productivity gap, from the other side. To meet these challenges an appropriate chip development platform and a corresponding design methodology are required. The Network-on-Chip (NoC) design paradigm is seen as a way of enabling the integration of exceedingly high number of computational and storage blocks in a single chip. In essence, NoC is a new approach to System-on-a-Chip (SoC) design. NoC based systems can accommodate multiple asynchronous clocking that many of today's complex SoC designs use. In other words, the NoC solution brings a networking method to on-chip communication and brings notable improvements over conventional bus systems. But its adoption and practical implementation faces important and unsolved issues related to design methodologies, test strategies, and dedicated CAD tools.
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