Low-Swing Signaling for FPGA Interconnect Power Reduction.

摘要

FPGAs are widely used in digital circuits implementation because of their lower non-recurring engineering cost and shorter time-to-market in comparison with ASICs. However, there are still area, performance, and energy efficiency gaps between FPGAs and ASICs. In this work, we propose a new FPGA architecture to narrow the energy efficiency gap. Since more than 60% of FPGA power is consumed in its interconnect, we focus on the global interconnect power reduction using low-swing signaling technique. To implement low-swing signaling, high-to-low and low-to-high voltage level converters are added to the basic architecture which consists of clusters with ten 6-input LUTs and uses single driver directional routing scheme. Simulation results on 20 largest MCNC circuits and 19 computational benchmarks confirm that the pro-posed architecture achieves an average of 13.5% total power reduction with the cost of less than 1% area and delay overhead.