Fast evaluation of VLSI interconnect structures using moment-matching methods.

摘要

For high performance digital circuits and systems, physical interconnect is rapidly becoming a dominant factor on overall performance. It is essential, therefore, that accurate models and evaluation techniques be developed to account for interconnect effects during design verification. The dominance of interconnect is particularly evident in systems incorporating multiple levels of integration, such as multi-chip module (MCM) systems. For an accurate interconnect evaluation of such a system, all the non-idealities associated with distributed interconnects must be considered, using models valid over the full bandwidth of high speed digital signals. Crosstalk, slow-wave propagation, and skin-effect are some of the potential non-idealities that must be dealt with. Such effects, in addition to presenting significant modeling challenges, are difficult to handle with typical digital-system verification tools.;This thesis discusses the design of accurate lumped-circuit models for non-ideal interconnects. The physical behavior of the various classes of distributed interconnect structures is considered in the design of the lumped approximations. Evaluation of the lumped models is efficiently achieved using the moment-matching method of Asymptotic Waveform Evaluation (AWE). Methods to ensure the reliability and accuracy of the AWE technique, in the context of interconnect evaluation, are described. In addition, efficient methodologies based on the proposed algorithms, for timing evaluation at the system level, are presented. Extensions to consider the effects of nonlinear driver and load models are also suggested. These address critical concerns in the design verification and test of the high-speed, high-performance systems of the future.