High-speed low-cost VLSI DSP algorithms based on novel fast convolutions and look-ahead pipelining structures.

摘要

The basic digital signal processing algorithms, such as FIR/DFT/DCT/DST/DWT, are implemented by VLSI hardware to realize high speed processing in video and image processing and communication systems. Efficient VLSI Digital Signal Processing (DSP) algorithms need to be developed for these applications. Although the capacity of VLSI technology has increased dramatically, high speed and low-cost VLSI Digital signal processing algorithms are crucial because they can lead to VLSI architectures with higher performance. Proposed research work on VLSI DSP based on fast DSP algorithms can significantly cut down the hardware cost and/or increase processing speed. Hardware efficient fast linear and cyclic convolution algorithms are developed for convolution-based VLSI DSP algorithms, such as FIR/DFT/DCT/DST/DWT.; All the high-speed VLSI DSP algorithms above are feed-forward circuits without feedback loops; these can be pipelined easily for speeding up the circuit. But for the applications with feedback loops, look-ahead pipeline algorithms are needed to reduce the loop bound. New pipeline methods are proposed for the high-speed implementation of parallel CRC, which can efficiently cut down the critical path and/or even save hardware cost, compared with previous parallel CRC algorithms in the literature. General Parallel Linear Feedback Shift Register (LFSR) Implementations are also developed for implementation of any high-speed parallel application with LFSR structures based on newly proposed look-ahead pipelining algorithms. The proposed design can efficiently eliminate the large fanout bottleneck and also reduce the critical path.; DNA sequence scanning is now a hot topic. Smith-Waterman algorithm is widely used in this field. However, traditional Smith-Waterman algorithm has feedback loops, which makes it hard to achieve high speed processing when direct unfolding algorithm is applied. A novel look-ahead pipelining algorithm is proposed to reduce the iteration bound. Unfolding algorithm can then be applied to achieve high throughput implementations.