Modeling, testing and analysis for delay defects and noise effects in deep sub-micron devices.

摘要

The performance of deep sub-micron devices can be affected by various parametric variations, manufacturing defects, noise, and modeling errors that are all statistical in nature. In this thesis, we propose a methodology to capture the effects of these statistical variations on circuit performance. It incorporates statistical information into timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise, or parametric variation sources. Next, we propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis.; Two applications are presented to demonstrate the methodology. First, we apply the proposed path selection technique for dynamic timing analysis considering power supply noise effects. The results indicate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis. In the second application, the framework is tuned to consider the effects of coupling capacitance between interconnects.; To provide a robust core engine for the above analysis, we developed two new statistical timing analysis algorithms. The first algorithm propagates probabilistic timing events from primary inputs through the circuit and obtains final probabilistic events (distributions) at all nodes. This new algorithm is deterministic and flexible in controlling run time and accuracy. Second, we present a false-path-aware statistical timing analysis framework. This tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths. It can also provide statistics such as probabilities of being true and critical for true paths.; Based on the newly proposed statistical timing analysis framework, we explore the problem of optimizing critical path selection given resource constraints. With a novel problem formulation and new theoretical results, we prove that the problem is computationally intractable. We then continue to demonstrate the effectiveness of several practical path selection strategies in both traditional and statistical domains. We show that by incorporating the two objectives of selecting the statistical longest path and of covering independent segments, better quality can be achieved for delay test and validation. Finally, we also propose a practical delay testing scheme to enhance test effectiveness by using multiple test sets with multiple clocks.