A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO.

摘要

The recent growth in the wireless communication industry has spurred a great interest in the CMOS RF circuits, the main reasons being the low cost of the CMOS process and the higher integration level made feasible by combining the RF transceiver and the digital baseband into a single chip. A frequency synthesizer is one of the critical blocks in the transceiver design. The problem of achieving both agility and good phase noise performance has always been the great challenge in designing the frequency synthesizer.; In this dissertation, a new architecture for the phase-locked loop (PLL) based frequency synthesizer is proposed and its performance is investigated. In the proposed architecture, the different feedback phases generated by the multiphase VCO are randomized. The main purpose is to remove the spurs resulting from the phase mismatch in the conventional multiphase fractional-N frequency synthesizer. It also helps achieve higher frequency resolution. In addition, it provides better noise shaping than the conventional multimodulus DeltaSigma fractional-N frequency synthesizer because of the smaller quanitized phase. The phase noise performance of the proposed architecture is analyzed. The result shows that the spur energy associated with the phase mismatch in the conventional multiphase fractional-N synthesizer is spread with the randomized technique.; The specific contributions of this work include: (1) proposing a new architecture using randomized multiphase VCO technique to remove the spur due to the phase mismatch from the multiphase VCO, and (2) providing better noise shaping than the conventional multimodulus DeltaSigma fractional-N synthesizer because of the smaller quantized phase.; To demonstrate the concept, a fully integrated 1.8-GHz frequency synthesizer with randomized multiphase VCO was designed. The prototype, implemented in a standard 0.6-mum CMOS technology, achieves -118 dBc/Hz phase noise at 1-MHz offset and exhibits close-in phase noise between -80 and -90 dBc/Hz up to the PLL loop bandwidth. The synthesizer has a frequency resolution of 10 Hz and dissipates 52 mW from a 3.3-V supply.