Helix -type compliant off -chip interconnect for microelectronic packaging.

摘要

The rapid advances in IC design and fabrication continue to challenge and push the microelectronic packaging industry in size, performance, cost, and reliability. The minimum feature size in IC components will reach the scale of 9 nm by the year of 2016 according to International Technology Roadmap for Semiconductors (ITRS) 2002, requiring the area-array off-chip interconnect pitch to be 50 gym. Under this fine pitch, not many off-chip interconnects can meet the requirements of reliability, performance, cost, and manufacturability. This bottleneck will limit the future progress of microelectronic industry. A new technology, which is called helix-type compliant off-chip interconnect, has been designed and developed to address some of the limitations with current off-chip interconnects. This research work covers full range of design, optimization, fabrication, assembly and reliability assessment of the novel interconnect technology through analytical, numerical and experimental investigations.;Two kinds of helix-type compliant interconnects, beta-helix and G-helix, have been designed for different applications. The fabrication of the helix-type compliant interconnects is based on the lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be integrated into wafer-level fine-pitch batch processing. The helix-type off-chip interconnects are expected to have good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. The geometry effects on the mechanical compliance and electrical parasitics have been studied analytically and numerically. However, it is found that the helix-type interconnect with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), optimization has been done. Moreover, physics-based predictive reliability models have been built to evaluate the effect of package weight on the free-standing compliant interconnect and the then-no-mechanical reliability. The heat removal capability of the helix-type compliant interconnect has also be studied. Finally a comprehensive design guideline for compliant off-chip interconnects has been established according to fabrication, design, optimization and thermo-mechanical-electrical analysis results.