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Design and development of stress-engineered compliant interconnect in microelectronic packaging.

机译:微电子封装中应力工程兼容互连的设计和开发。

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摘要

With the increased demand for lower cost, smaller profile and better performance in microelectronic devices, the feature size of integrated circuits (ICs) is continuously reduced into sub-micron scale. An effective solution to electronic packaging, especially the chip-to-substrate interconnection technology, must be provided to fit the rapid development of semiconductor industry well. An innovative technology, called stress-engineered compliant interconnect, is being developed to meet the requirements of International Technology Roadmap for Semiconductor (ITRS) requirements for year 2016 and even beyond. The thin film metal is stress-engineered during sputtering deposition on the wafer, patterned by photolithography, and later curls up automatically due to the intrinsic stress gradient through the thickness. The unique fabrication of this interconnect is cost competitive and can be easily integrated into wafer-level packaging (WLP).; The stress-engineered compliant interconnect is expected to have a different thermo-mechanical performance, compared with the traditional rigid C4 interconnect. The new room-temperature assembly approaches have been developed with respect to the fine pitch and high compliance of this stress-engineered compliant interconnect. A suitable packaging material is selected based on the property characterization. To understand the thermo-mechanical reliability of this compliant interconnect, test vehicles have been fabricated, assembled and subjected to thermal cycling test. The thermo-mechanical reliability of the contact interconnects is assessed through the measurement of electrical resistance during thermal cycling. In parallel to the experiments, the finite-element models have been developed to predict the thermo-mechanical reliability of the compliant interconnect assembly. The sliding contact reliability is also considered for the free-air non-soldered assembly under the constant normal compressive load and the cyclic tangential frictional load caused by the cyclical temperature excursion. In addition, a n alternative compliant interconnect, called ‘J-Spring’, has also been proposed to improve the in-plane compliance. General design guidelines of the stress-engineered compliant interconnect reliability are proposed.
机译:随着对微电子器件中低成本,更小外形和更好性能的需求的增加,集成电路(IC)的特征尺寸不断缩小到亚微米级。必须提供一种有效的电子封装解决方案,尤其是芯片到基板的互连技术,以适应半导体行业的快速发展。正在开发一种称为压力工程兼容互连的创新技术,以满足2016年及以后的国际半导体技术路线图(ITRS)要求。薄膜金属是在晶片上进行溅射沉积期间进行应力工程处理的,通过光刻进行图案化,然后由于厚度方向上的固有应力梯度而自动卷曲。这种互连的独特制造具有成本竞争力,并且可以轻松集成到晶圆级封装(WLP)中。与传统的刚性C4互连相比,应力工程兼容互连有望具有不同的热机械性能。针对这种应力工程兼容互连的精细间距和高一致性,已经开发出了新的室温组装方法。基于特性表征选择合适的包装材料。为了了解这种兼容互连的热机械可靠性,已经制造,组装并进行了热循环测试的测试车辆。接触互连的热机械可靠性通过热循环过程中的电阻测量来评估。与实验并行,已经开发了有限元模型来预测柔性互连组件的热机械可靠性。对于自由空气非焊接组件,在恒定的法向压缩载荷和由循环温度偏移引起的循环切向摩擦载荷下,也要考虑滑动接触的可靠性。此外,还提出了一种名为“ J-Spring”的n替代兼容互连,以改善平面内兼容性。提出了应力工程兼容互连可靠性的一般设计准则。

著录项

  • 作者

    Ma, Lunyu.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Mechanical.; Engineering Packaging.
  • 学位 Ph.D.
  • 年度 2003
  • 页码 205 p.
  • 总页数 205
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 机械、仪表工业;包装工程;
  • 关键词

  • 入库时间 2022-08-17 11:44:41

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