The Integration of Nearthreshold and Subthreshold CMOS Logic for Energy Minimization.

摘要

With the rapid growth in the use of portable electronic devices, more emphasis has recently been placed on low-energy circuit design. Digital subthreshold complementary metal-oxide-semiconductor (CMOS) circuit design is one area of study that offers significant energy reduction by operating at a supply voltage substantially lower than the threshold voltage of the transistor. However, these energy savings come at a critical cost to performance, restricting its use to severely energy-constrained applications such as microsensor nodes. In an effort to mitigate this performance degradation in low-energy designs, nearthreshold circuit design has been proposed and implemented in digital circuits such as Intel's energy-efficient hardware accelerator.;The application spectrum of nearthreshold and subthreshold design could be broadened by integrating these cells into high-performance designs. This research focuses on the integration of characterized nearthreshold and subthreshold standard cells into high-performance functional modules. Within these functional modules, energy minimization is achieved while satisfying performance constraints by replacing non-critical path logic with nearthreshold and subthreshold logic cells. Specifically, the critical path method is used to bind the timing and energy constraints of the design. The design methodology was verified and tested with several benchmark circuits, including a cryptographic hash function, Skein. An average energy savings of 41.15% was observed at a circuit performance degradation factor of 10. The energy overhead of the level shifters accounted for at least 8.5% of the energy consumption of the optimized circuit, with an average energy overhead of 26.76%. A heuristic approach is developed for estimating the energy savings of the optimized design.