On multiple-valued static CMOS memory cells.

摘要

An overview of the existing techniques for the design of multiple-valued memory reveals several methods closely related to the design of voltage based and current based memory cells. This thesis proposes modifications in the current based memory cell by lowering the transistor count, thereby enhancing performance by reducing the effective area and power dissipation and increasing the speed of operation. A modification has also been proposed for the voltage based memory cell by adding a transmission gate at the output in order to enhance the understandability of its operation. This thesis also compares four different types of voltage based and current based memory cells in terms of device count, standby power and setup and hold times. The results show that voltage mode circuits have low and in some case no standby power. However the current mode circuits have the advantage of operating at reduced power supply voltages. All the designs were implemented in spice (1.5μ technology).