A study of electron transport in the inversion layer of advanced silicon carbide power MOSFETs.

摘要

This dissertation addresses the study of carrier transport in advanced silicon carbide (SiC) power MOS devices. The research focuses on the fabrication, electrical characterization and modeling of advanced SiC devices, including self-aligned lateral MOSFETs, novel surface and buried-channel DiMOS (Double-Implanted MOSFET) devices with particular emphasis on their utilization for power switching applications. The research emphasizes the characterization of electron transport in SiC inversion layers with the development of a physics-based, 2-D quantum-mechanical model to explain the IDS - VGS, gm - VGS device electrical characteristics and the mobility behaviors (muFE, mucon). We also describe a self-aligned device fabrication sequence, an investigation of SiC/SiO 2 interface state density in the inversion regime with a subthreshold-slope method and the charge pumping technique, and the extraction of modeling parameters in these advanced SiC power devices.; In the self-aligned process for the fabrication of DiMOS and lateral MOSFETs, we employ C/Al co-implantation into the p+ regions and phosphorus into n+ regions to improve the activation of implants and reduce the contact resistance while maintaining a low thermal budget.; Interface trap density is a key issue in SiC MOS devices. A high-quality dielectric on a SiC MOSFET is difficult to achieve because of high oxide charges and the large density of interface states at the SiC/SiO2 interface near the conduction band edge. In order to provide an effective insight into the nature of this SiC/SiO2 interface near the conduction band edge, we have employed a subthreshold-slope method to study interface trap density in the inversion region of SiC MOSFETs. The interface trap distributions are extracted for 4H and 6H MOSFETs fabricated on ion-implanted surfaces. The interface trap densities near the conduction band edge are found to be in the range of 5 x 1012∼3 x 1013 cm-2eV-1 for SiC MOSFETs with thermal oxidation process, and 1011∼4 x 1012 cm-2eV-1 for SiC MOSFETs with nitridation anneal process. In addition, we use charge-pumping to characterize the SiC/SiO 2 interface and extract the average midgap interface trap density on 4H-SiC MOSFETs. We employ CGC - VGS measurements to extract oxide thickness and TLM measurements to extract contact resistance for 4H-SiC MOSFETs. In particular, we determine the transconductance (g m), the field-effect mobility (muFE) and conductance mobility (mucon). We compare these measurements with a theoretical model for electron transport in the inversion layer, and obtain 3% accuracy from subthreshold to very strong inversion for a range of substrate biases.; We develop a physics-based, 2-D quantum-mechanical, mobility model for SiC MOS devices, which includes the combined effects of surface roughness and Coulomb scattering. The high density of interface traps near the conduction band edge in SiC MOSFETs precludes the designation of a fixed device threshold voltage and requires the development of a device model to account for this behavior. The Coulomb scattering is modeled with interface traps and fixed oxide charge, while surface roughness assumes a random distribution of spatial fluctuations with a Gaussian distribution. The model is employed to explain the conduction characteristics and mobility behavior of 6H and 4H-SiC MOSFETs at various substrate biases.