This work focuses on the development of accurate and efficient performance parameter macro-models for use in the synthesis of analog circuits. Once constructed the mathematical models may be used as substitutes for full SPICE simulation, providing efficient computation of performance parameter estimates. In this thesis, we explore various modeling architectures, develop and apply two unique sampling methodologies for adaptively improving model quality, and attempt to apply the sizing rules methodology in order to perform dimensional reduction and ensure proper operation of analog circuits.; In order to properly create an analog performance model, a training data set is needed to create the model, and an independent validation data set is needed to verify the accuracy of the model. The training and validation data sets are comprised of discretely sampled points in the design space. Various methods exist for generating these sample points. A static sampler does not take into account the shape of the function under scrutiny, whereas an adaptive sampler strives to reduce modeling error through strategic placement of sample points. Two unique adaptive sampling methodologies are developed in this work and are applied to various analog circuit performance metrics. The first adaptive sampler is based on piecewise-linear models while the second sampler uses more complex non-linear pseudo-cubic splines. It is shown experimentally that both adaptive samplers are capable of improving maximum modeling errors for various performance metrics and analog topologies. Strategic placement of costly sample points improves model quality while reducing the time needed to create the performance models. Adaptive sampling also alleviates human intervention during model construction, realizing an automatic framework for sampling and modeling performance parameters.; The sizing rules method and feasibility region modeling are analyzed and applied to analog performance macro-modeling in an attempt to automatically reduce the dimensionality of the design space, simplify performance parameter behavior, and ensure proper DC biasing of analog circuits. A feasibility region is a portion of the design space satisfying design space and electrical space inequality constraints generated by the sizing rules method. Experimental evidence indicates that the sizing rules method alone does not sufficiently constrain a circuit to facilitate the creation of accurate analog performance macro-models. Additional, manually derived design constraints are required to enable the development of accurate performance parameter models.
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