Copper electrodeposition in the 'Dual Damascene' process for the metallization of semiconductor interconnects has recently become the mainstay for fabricating high-end microprocessors. The key to the successful implementation of this technology is an empirically formulated mixture of additives that inhibit deposition on the more accessible wafer surface and enhance plating at the bottom of the vias ('bottom-up' fill). Although the exact compositions of the commercial additives mixtures are proprietary, all systems incorporate chloride ions [Cl-], an inhibitor [e.g., polyethylene glycol---PEG], and an accelerator [e.g., bis(3-sulfopropyl) disulfide---SPS].; In this work, a time-dependent transport-adsorption-interaction model for the additives is developed in order to characterize their role in the 'bottom-up' fill. The model is based on analyzing the diffusional transport and adsorption of the additives, in conjunction with their interactions. All model parameters are determined experimentally by measuring the steady-state and transient copper deposition kinetics in the presence of additives. The effect of the local electrode area reduction during the via-fill on the additives distribution is incorporated in the via-fill simulations. The analysis indicates that a defect-free via-fill requires an additives mixture with special characteristics: an inhibiting additive (PEG) that is transport limited but adsorbs fast, and an accelerator (SPS) that diffuses rapidly but adsorbs slowly by displacing the PEG, thereby gradually counteracting the inhibition provided by the PEG. The significance of the additives transport-adsorption process during the 'bottom-up' fill of sub-100 nm vias is explained, and the effect of the process parameters, such as the additives composition and the applied potential, is analyzed.; Semi-analytical scaling analysis indicates that the additives transport-adsorption process occurs over a time-scale that is comparable to the via-fill duration in high aspect ratio features, thereby underscoring the importance of such transient effects in the via-fill of next generation sub-100 nm geometries. Analysis is also applied to vias with sloping sidewalls to characterize the effect of the via geometry on the additives distribution, and therefore, on the via-fill performance. Qualitative agreement with experimental observations is noted.; The 'microscopic' single via model is extended to characterize 'macroscopic' wafer-scale processes. The simulated wafer-scale current response is in qualitative agreement with experimental measurements.
展开▼
