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The Influence of Impurities and Metallic Capping Layers on the Microstructure of Copper Interconnects.

机译:杂质和金属覆盖层对铜互连微结构的影响。

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摘要

As copper interconnects have scaled to ever smaller dimensions on semiconductor devices, the microstructure has become increasingly detrimental for performance and reliability. Small grains persist in interconnects despite annealing at high temperatures, leading to higher line resistance and more frequent electromigration-induced failures. Conventionally, it was believed that impurities from the electrodeposition pinned grain growth, but limitations in analytical techniques meant the effect was inferred rather than observed.;Recent advances in analytical techniques, however, have enabled this work to quantify impurity content, location, and diffusion in relation to microstructural changes in electroplated copper. Surface segregation of impurities during the initial burst of grain growth was investigated. After no surface segregation was observed, a microfluidic plating cell was constructed to plate multilayer films with regions of intentionally high and low impurity concentrations to determine if grain growth could be pinned by the presence of impurities; it was not.;An alternate mechanism for grain boundary pinning based on the texture of the seed layer is proposed, supported by time-resolved transmission electron microscopy and transmission electron backscatter diffraction data. The suggested model posits that the seed in narrow features has no preferred orientation, which results in rapid nucleation of subsurface grains in trench regions prior to recrystallization from the overburden down. These rapidly growing grains are able to block off several trenches from the larger overburden grains, inhibiting grain growth in narrow features.;With this knowledge in hand, metallic capping layers were employed to address the problematic microstructure in 70nm lines. The capping layers (chromium, nickel, zinc, and tin) were plated on the copper overburden prior to annealing to manipulate the stress gradient and microstructural development during annealing. It appeared that regardless of as-plated stress, nickel capping altered the recrystallized texture of the copper over patterned features. The nickel capping also caused a 2x increase in the number of advantageous 'bamboo' grains that span the entire trench, which effectively block electromigration pathways. These data provides a more fundamental understanding of manipulating the microstructure in copper interconnects using pre-anneal capping layers, and demonstrates a strategy to improve the microstructure beyond the capabilities of simple annealing.
机译:由于铜互连已在半导体器件上按比例缩小到越来越小的尺寸,因此微结构对性能和可靠性的损害越来越大。尽管在高温下退火,小晶粒仍会保留在互连中,从而导致更高的线路电阻和更频繁的电迁移引起的故障。通常认为,电沉积中的杂质会阻碍晶粒的生长,但是分析技术的局限性意味着可以推断而不是观察到这种影响。然而,分析技术的最新进展已使这项工作能够量化杂质含量,位置和扩散与电镀铜的微观结构变化有关。研究了晶粒长大初期的过程中杂质的表面偏析。在未观察到表面偏析之后,构建了一个微流控镀槽,可以镀覆多层膜,该膜的杂质浓度有意地高和低,以确定是否可以通过杂质的存在来抑制晶粒的生长。在时间分辨透射电子显微镜和透射电子背散射衍射数据的支持下,提出了基于晶种层织构的另一种晶界钉扎机制。建议的模型假定狭窄特征的晶种没有优选的取向,这会导致从覆盖层向下重结晶之前,沟槽区域中的地下晶粒快速成核。这些快速生长的晶粒能够阻挡较大的覆盖层晶粒的多个沟槽,从而抑制晶粒在狭窄特征中的生长。掌握了这一知识之后,金属覆盖层被用于解决70nm线中存在问题的微观结构。在退火之前,将覆盖层(铬,镍,锌和锡)镀在覆铜层上,以控制退火过程中的应力梯度和微结构发展。似乎无论镀应力如何,镍覆盖都会改变图案特征上铜的重结晶织构。镍封盖还导致横跨整个沟槽的有利的“竹”晶粒数量增加了2倍,从而有效地阻止了电迁移路径。这些数据为使用预退火盖层处理铜互连中的微结构提供了更基本的理解,并演示了一种改善微结构的策略,其范围超出了简单退火的能力。

著录项

  • 作者

    Rizzolo, Michael.;

  • 作者单位

    State University of New York at Albany.;

  • 授予单位 State University of New York at Albany.;
  • 学科 Nanotechnology.;Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 2014
  • 页码 201 p.
  • 总页数 201
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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