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Characterization of carrier transport properties in strained crystalline Si wall-like structures as a function of scaling into the quasi-quantum regime.

机译:应变晶体硅壁状结构中的载流子输运性质的表征,是按比例缩放到准量子态的函数。

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摘要

The transport characteristics of both electrons and holes through narrow constricted "wall-like" Silicon (Si) long-channels that were surrounded by a thermally grown SiO2 layer was investigated. As a result of the existence of fixed oxide charges in the thermally grown SiO2 layer and the Si/SiO2 interface, the effective Si cross-sectional wall widths were considerably narrower than the actual physical widths, due the formation of depletion regions from all sides. The physical height of the crystalline-Si structures was ~1500nm, and the widths were incrementally scaled down from ~200nm to ~20nm. These nanostructures were configured into a metal-semiconductor-metal (MSM) device configuration that was isolated from the substrate. Dark currents, dc-photo-response, and time response measurements using a mode-locked femtosecond laser, were used in the study. In the narrowest wall devices, a considerable increase in conductivity was observed as a result of higher carrier mobilities due to lateral constriction. The strain effects, which include the reversal splitting of light- and heavy- hole bands as well as the decrease of conduction-band effective mass by reduced Si bandgap energy, are formulated in our microscopic model for explaining the experimentally observed enhancements in both conduction- and valence-band mobilities with reduced Si wall thickness. Specifically, the enhancements of the valence-band and conduction-band mobilities are found to be associated with different aspects of physical mechanisms. The role of the biaxial strain buffering depth is elucidated and its importance to the scaling relations of wall-thickness is reproduced theoretically, i.e., 1/L2 for electrons and 1/L for holes.
机译:研究了电子和空穴通过被热生长的SiO2层包围的狭窄狭窄的“壁状”硅(Si)长沟道的传输特性。由于在热生长的SiO2层和Si / SiO2界面中存在固定的氧化物电荷,有效的Si横截面壁宽比实际的物理宽度要窄得多,这是因为从各个侧面形成了耗尽区。晶体硅结构的物理高度为〜1500nm,宽度从〜200nm逐渐缩小至〜20nm。这些纳米结构被配置为与衬底隔离的金属-半导体-金属(MSM)器件配置。在这项研究中,使用了锁模飞秒激光器的暗电流,直流光响应和时间响应测量。在最窄的壁装置中,由于侧向收缩而导致较高的载流子迁移率,导致电导率显着增加。在我们的微观模型中,提出了应变效应,包括光和重空穴带的反向分裂以及由于硅带隙能量的降低而导致的导带有效质量的降低,以解释实验观察到的两种传导增强的作用。硅壁厚度减小的价带迁移率。具体而言,发现价带和导带迁移率的增强与物理机制的不同方面相关。阐明了双轴应变缓冲深度的作用,并且从理论上再现了其对壁厚的比例关系的重要性,即电子为1 / L2,空穴为1 / L。

著录项

  • 作者

    Mayberry, Clay Scott.;

  • 作者单位

    The University of New Mexico.;

  • 授予单位 The University of New Mexico.;
  • 学科 Nanoscience.;Electrical engineering.
  • 学位 Ph.D.
  • 年度 2016
  • 页码 104 p.
  • 总页数 104
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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