Power management of integrated analog filters.

摘要

This thesis investigates possible design strategies that result in attractive power dissipation savings in active filter designs. The first design strategy is related to the syllabic companding technique and its modification in the presence of the interferers. It proposes to distribute AGC operations throughout the filter's internal nodes and to amplify weak signals as interferers are attenuated. This results in relaxed dynamic range requirements for the latter stages of the filter, which consequently allow us to minimize their power dissipation and chip area. In order to implement these AGC operations without disturbing the output of the filter, a new practical implementation of the syllabic companding technique is introduced; only two filter paths are used, and their usable dynamic range is modified by alternatively changing the gain settings of the filters according to the signal reception conditions at hand.; The second design strategy proposes to reduce the high power dissipation of the filter dynamically, required for the worst-case reception conditions, as signal reception gets better. A general dynamic impedance scaling technique is proposed which allows us to increase the noise floor and consequently reduce the power dissipation of the filter dynamically without disturbing the output of the filter.; These two design strategies result in very attractive power savings, which is appealing for today's growing portable applications. The two techniques are implemented in two low voltage, active-RC filters both designed for a zero-IF GSM receiver. Even though the filters are designed for a specific application, the techniques are of general validity. The two filters are fabricated in a standard 0.18-mum CMOS process and use a 1.2 V power supply.