The development of electronic devices is based on strict weight and size requirements. Smaller, lighter, and higher capacity devices at low costs are normal demands nowadays. In order to achieve this goal, electronic packaging plays a major role in the electronic industry. The thickness of silicon wafers affects directly the package size, so that the thinner the wafer the smaller the electronic package. The optimization of the grinding parameters for silicon wafers is necessary in order to reduce the likelihood of residual stresses and crack nucleation in the machined surface and improve the reliability of electronic packages. This thesis describes numerical simulations performed to characterize the back grinding process for bare silicon wafers and Through-Silicon Via (TSV) wafers using the finite element code ABAQUS. The numerical simulations involved studying the characteristics of the grinding process at three different levels: the residual stresses on the ground surface in bare silicon as well as TSV wafers, the heat generated from the grinding process due to the friction, and the wafer warpage as a result of the film stresses due to the grinding process. In chapters two, three and four, the grinding of the two wafer types was performed by simulating the motion of a diamond particle cutting through successive silicon and TSV layers. The silicon material was modeled using orthotropic elasticity and isotropic plasticity, while the copper vias were modeled using isotropic elasticity and Johnson Cook plasticity. The Poly-Ethylene Terephthalate (PET) material used as a backing tape for the silicon wafer was modeled using the Mooney Rivlin hyper-elastic model. The computed residual stresses and the plastic deformation in the superficial layer of the ground wafer were compared with experimental values from the literature and good correlation was observed. Chapter five describes the work performed to simulate the heat generated during the back grinding process for silicon wafers. The grinding of a silicon wafer with a thickness of 60 mum mounted on a silicon carrier wafer using bond adhesive material was simulated. The heat generated is due to the friction between the grinding wheel and the backside of the silicon wafer, by simulating the grinding process on the macro level. The computed temperature change due to friction in the wafer was compared with experimental and numerical values from the literature, and showed good correlation. Chapter six describes the work performed to simulate the silicon wafer warpage as a function of the wafer thickness and the film stresses. The model developed accounts for the silicon anisotropy to better simulate the deformation. The computed values of the warpage were compared with experimental data, and showed good correlation. The simulation results from the models developed can be used to better understand the local stresses and strain fields in both bare silicon and TSV wafers, the heat generated from the grinding process and the wafer warpage due to the film stresses, and quantify the characteristics of the process of grinding silicon wafers for electronic devices fabrication.
展开▼
