Printed circuit boards may experience mechanical drop shocks at any time during their life cycle. This thesis investigates the response of several bare and BGA populated circuit boards to drop shocks. The study correlates computer simulations with experimental data, and attempts to develop a failure criterion for pad tear out. Furthermore, the work shows that the reaction force on the component side of the solder joint stays relatively constant during the simulation and over several drop heights. It also shows that the solder stress decreases significantly for thinner boards because the thinner, more flexible boards can conform to the assembly's profile. The results for a JEDEC-equivalent board show that at low JEDEC drop specifications, linear time marching and shock response analyses closely follow nonlinear time marching analysis. This is expanded to investigate the difference in solder stresses on a populated board at several drop heights, using the various solution methods.
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