Automated synthesis and null cycle reduction optimization for asynchronous null convention circuits using industry-standard CAD tools.

摘要

This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts. This dissertation is organized into two papers, as described below.; The first paper presents an automated NCL circuit synthesis algorithm and tool, which is loosely based on the Threshold Combinational Reduction (TCR) method for designing NCL circuits by hand. The paper develops algorithms for NCL logic optimization and technology mapping, which are utilized to produce delay and area optimized NCL circuits, starting from standard Boolean behavioral/dataflow VHDL combinational circuit descriptions.; The second paper discusses an Automated NULL Cycle Reduction (ANCR) tool, developed to enhance NCL circuit throughput, which is especially useful for slow pipeline stages and feedback loops. ANCR can be applied to NCL circuits with both dual-rail and quad-rail I/Os, utilizing either full-word or bit-wise completion.