Challenges and solutions for fault tree analysis arising from automatic fault tree generation: Some milestones on the way

摘要

In the development of embedded systems, safety and reliability are important quality characteristics. Fault tree analysis is often used to determine these characteristics. Fault tree analyses are usually performed manually. Taking into account the high complexity of today's technical systems this is in many cases not possible within the limits of existing time and budget constraints. Furthermore, completeness and precision of the results are neither guaranteed nor systematically provable. The automatic generation of generalized fault trees permits saving time and effort and increases the quality of the results. Completeness, correctness, and consistency of the generated fault trees are guaranteed. We have developed, apart from other approaches, a fault tree generation tool for electronic circuits that generates fault trees based on the standardized electronic design interchange format (EDIF). This tool has been used e.g., to analyze failure situations in industrial automation applications. As automatic fault tree generation makes possible analyzing even very large systems, existing algorithms for calculation of reliability figures needed considerable improvement regarding performance. We implemented a BDD-based algorithm to solve that problem. Furthermore, our tools have been verified by a Back-to-back test to support use in certification of safety critical systems.