On the modeling and testing of VHDL behavioral descriptions ofsequential circuits

摘要

A new automatic test generation principle based on a formalnmodeling of VHDL behavioral descriptions is proposed. Using to thenfinite state machine representation and a formalism close to that ofnPetri nets, the authors define two models which represent all thenconcepts associated with a VHDL description. They then propose angeneration principle which uses both forward and backward timenprocessing