Downscaling issues in polycrystalline silicon TFTs

摘要

Polycrystalline silicon (polysilicon) thin film transistors (TFTs) are key devices for future system-on-panel applications [1]. Circuit performance improvements can be obtained by reducing channel length to 1 μm or less and, therefore, short channel effects in scaled down polysilicon TFTs will have to be controlled in order to allow proper operation of the devices. In this work we will review the effects of downscaling the device geometry and, in particular, the parasitic resistance effects, the kink effect and the threshold voltage variations will be discussed in some detail by combining experimental measurements and two-dimensional numerical simulations.