Systolic VLSI implementations of a Galois field arithmeticalgorithms

摘要

Two systolic architectures that implement the algorithms fornmultiplication, division and exponentiation operations in GF(2^mn) are presented. The architectures are systolic and capable ofnproducing a new result every clock cycle. Two prototype VLSI chips,nSIGMA (for multiplication/division) and ACE (for exponentiation), havenbeen designed using 2 micron CMOS technology. Both SIGMA and ACE arenimplemented for the GF(2⁴) and are programmable to selectnbetween different irreducible polynomials. The chips can yield ancomputational rate of 40 million operations per second