Vertical and in-plane electrical transport in InAs/InP semiconductor nanostructures

摘要

Vertical and in-plane electrical transport in InAs/InP semiconductors wires and dots have been investigated by conductive atomic force microscopy (C-AFM) and electrical measurements in processed devices. Localized Ⅰ-Ⅴ spectroscopy and spatially resolved current images (at constant bias), carried out using C-AFM in a controlled atmosphere at room temperature, show different conductances and threshold voltages for current onset on the two types of nanostructures. The processed devices were used in order to access the in-plane conductance of an assembly with a reduced number of nanostructures. On these devices, signature of two-level random telegraph noise (RTN) in the current behavior with time at constant bias is observed. These levels for electrical current can be associated to electrons removed from the wetting layer and trapped in dots and/or wires. A crossover from conduction through the continuum, associated to the wetting layer, to hopping within the nanostructures is observed with increasing temperature. This transport regime transition is confirmed by a "temperature-voltage" phase diagram.