Surrounding gate MOSFETs S/D design for 28 nm technology

摘要

A gate-last MOSFET has been suggested for 32 nm node CMOSFET, where the integration of a high-k gate dielectric and a metal gate electrode becomes essential to meet the transistor performance requirement. The gate-last MOSFET has been demonstrated as an effective integration scheme to avoid thermal instability and workfunction mismatch issues [1–2]. Even though feasibility of such gate structure for the 32 nm node MOSFET have been recently demonstrated, a comprehensive study on the performance impact of the gate structures has yet to be reported. In this work, we investigate the effect of the gate structures on the transistor performance and optimize the source/drain overlap to the gate for a 16 nm MOSFET using TCAD simulation.