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Understanding limits to conductivity of metal nanowires

机译:了解金属纳米线的电导率限制

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Reduced conductivity in sub-100nm metal wires used as interconnects is a performance limiting factor in integrated circuits. In order to understand the sources of conductivity degradation with the aim of optimizing metal nanowire conductivity, we have analyzed potential sources of electron momentum loss, including surface roughness scattering, grain boundary reflection and interactions with Ta liner layers. Based on the roughness spectrum of metal films, we conclude that primarily specular scattering should be achievable at metal/dielectric interfaces for Cu technology. Using non-equilibrium Green's function methods, we find substantial reflection at Cu and Ag grain boundaries and find that both the change in grain orientation and disorder in the boundary contribute significantly to reflectivity. Using the same approach for Cu/Ta interfaces, we predict substantial conductivity degradation due to electron interactions with thin liner layers. Based on our analyses, we conclude by suggesting promising directions for maximizing conductivity as interconnect dimensions shrink further below 100nm.
机译:用作互连的100nm以下金属线的电导率降低是集成电路的性能限制因素。为了了解以优化金属纳米线电导率为目标的电导率下降的原因,我们分析了电子动量损​​失的潜在原因,包括表面粗糙度散射,晶界反射以及与Ta衬里层的相互作用。根据金属膜的粗糙度谱,我们得出结论,对于Cu技术,主要应在金属/电介质界面处实现镜面散射。使用非平衡格林函数方法,我们发现在铜和银晶粒边界处有大量反射,并且发现晶粒取向的变化和边界中的无序性都对反射率有显着影响。对Cu / Ta界面使用相同的方法,我们预测由于与薄衬层的电子相互作用,导电性将大大降低。根据我们的分析,我们得出结论,提出了在互连尺寸进一步缩小到100nm以下时,最大化导电性的有希望的方向。

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