HECC Goes Embedded: An Area-Efficient Implementation of HECC

摘要

In this paper we describe a high performance, area-efficient implementation of Hyperelliptic Curve Cryptosystems over GF(2~m). A compact Arithmetic Logic Unit (ALU) is proposed to perform multiplication and inversion. With this ALU, we show that divisor multiplication using affine coordinates can be efficiently supported. Besides, the required throughput of memory or Register File (RF) is reduced so that area of memory/RF is reduced. We choose hyperelliptic curves using the parameters h(x) = x and f(x) = x~5 + f_3x~3 + x~2 + f_0. The performance of this coprocessor is substantially better than all previously reported FPGA-based implementations. The coprocessor for HECC over GF(2~(83)) uses 2316 slices and 2016 bits of Block RAM on Xilinx Virtex-II FPGA, and finishes one scalar multiplication in 311 μs.