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Flexible hardware architecture for ECC/HECC based crytography
Flexible hardware architecture for ECC/HECC based crytography
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机译:灵活的硬件架构,用于基于ECC / ECC的加密
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摘要
A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.
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