Fabrication process controlled pre-existing and charge - discharge effect of hole traps in NBTI of high-k / metal gate pMOSFET

机译：高k /金属栅pMOSFET的NBTI中空穴陷阱的制备工艺控制

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This study aims to investigate the application of a technique to separate bulk hole trap effects from interface state degradation in NBTI to understand hole traps behavior including MOSFET fabrication process dependence. A gate last process is used to fab

机译：这项研究旨在研究一种将NBTI中界面状态退化与体空穴陷阱效应分离的技术的应用，以了解空穴陷阱行为，包括MOSFET制造工艺的依赖性。最后浇口工艺用于制造

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来源
《Programmable Logic, 2008 4th Southern Conference on; Phoenix,AZ,USA》||P.655-656|共2页
会议地点 PhoenixAZUSA
作者
Sato; M.; Tamura; C.; Yamabe; K.; Shiraishi; K.; Yamada; K.; Hasunuma; R.; Aoyama; T.; Nara; Y.; Ohji; Y.;
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原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
hafnium compounds; high-k dielectric thin films; hole traps; interface states; interstitials; nitridation; power MOSFET; rapid thermal annealing; titanium compounds; HfSiON-TiN; RTA; charge-discharge effect; gate last process; gate stacks; hole injection; hole traps; in;

机译：compounds化合物;高k介电薄膜;空穴陷阱;界面态;间隙;氮化;功率MOSFET;快速热退火;钛化合物; HfSiON-TiN; RTA;充放电效应;后栅极工艺;栅极叠层;空穴注入陷阱;

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专利

1. 105 Nm Gate Length Pmosfets With High-k And Metal Gate Fabricated In A Si Process Line On 200 Mm Geoi Wafers [J] . C, Le Royer, L, Solid-State Electronics . 2008,第9期

机译：在200 Mm Geoi晶圆的Si工艺生产线中制造的具有高k和金属栅极的105 Nm栅极长度Pmosfets
2. High-performance organic nano-floating-gate memory devices based on graphite nanocrystals as charge-trapping elements and high-k Ta2O5 as a controlled gate dielectric [J] . Min-Kun Dai, Tai-Yuan Lin, Min-Hua Yang Journal of Materials Chemistry, C. materials for optical and electronic devices . 2014,第27期

机译：基于石墨纳米晶体作为电荷俘获元素和高k Ta2O5作为受控栅介质的高性能有机纳米浮栅存储器件
3. Impact of Trap Behavior on Random Telegraph Noise in High-k/Metal Gate pMOSFETs [J] . Kao Tsung-Hsien, Chang Sheng-Po, Chang Shoou-Jinn Journal of Nanoelectronics and Optoelectronics . 2018,第4期

机译：陷阱行为对高k /金属栅极PMOSFET随机电报噪声的影响
4. Fabrication process controlled pre-existing and charge - discharge effect of hole traps in NBTI of high-k / metal gate pMOSFET [C] . Sato M., Tamura C., Yamabe K., IEEE International Reliability Physics Symposium . 2008

机译：制造过程控制了高K /金属栅极PMOSFET的NBTI孔陷阱的预先存在和充放电效果
5. Enhanced hot-hole degradation and negative bias temperature instability (NBTI) in p+-poly PMOSFETs with oxynitride gate dielectrics. [D] . Chen, Yuh-Yue. 1999

机译：具有氧氮化物栅极电介质的p + -poly PMOSFET中的热孔退化和负偏压温度不稳定性（NBTI）增强。
6. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs [O] . H. Hussin, N. Soin, M. F. Bukhori, -1

机译：栅堆叠结构和工艺缺陷对32 nm工艺节点PMOSFET中NBTI可靠性的高k介电依赖性的影响
7. Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor [O] . Rishu Chaujar, Mekonnen Getnet Yirak 2021

机译：接口陷阱电荷对无线双金属栅极高k门的影响纳米线FET基于Alzheimer Biosensor

Fabrication process controlled pre-existing and charge - discharge effect of hole traps in NBTI of high-k / metal gate pMOSFET

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