首页> 外文会议>Proceedings of the 27th European solid-state device research conference >Fabrication of 0.1#mu#m MOSFET with Super Self-Aligned Ultrashallow Junction Electrods using Selective Si_(1-x)Ge_x CVD
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Fabrication of 0.1#mu#m MOSFET with Super Self-Aligned Ultrashallow Junction Electrods using Selective Si_(1-x)Ge_x CVD

机译:使用选择性Si_(1-x)Ge_x CVD制备具有超自对准超浅结电极的0.1#μ#m MOSFET

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Fabrication process of 0.1#mu#m MOSFET's were developed with Super Self-aligned ultra-Shallow junction Electrode(S~3EMOSFET)by utilizing in-situ impurity doped Si_(1-x)Ge_x slective epitaxy on the source/drain regions at 550 deg C by CVD. NOrmal saturation characteristics were observed and the threshold voltage scarcely showed a shift with the gate length, which means that the short channel effect is greatly suppressed in the S~3EMOSFET. Further improvements of the current drivability were performed by annealing and selective tungsten growth. The results show very high potentials of this device for an ultrasmall MOSFET, because theeffective channel length is almost the same as the fabricated gate length and the source/drain junctions are ectremely shallow.
机译:通过在550°C的源/漏区上采用原位掺杂Si_(1-x)Ge_x外延选择性外延技术,采用超自对准超浅结电极(S〜3EMOSFET)开发了0.1#μ#m MOSFET的制造工艺。 CVD测定。观察到标称饱和特性,并且阈值电压几乎不随栅极长度变化,这意味着S〜3EMOSFET中的短沟道效应得到了极大的抑制。通过退火和选择性钨生长,进一步提高了电流驱动性能。结果表明,该器件具有极高的潜力,可用于超小型MOSFET,因为有效沟道长度几乎与制造的栅极长度相同,并且源极/漏极结非常浅。

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