Optimizing galvanic pulse plating parameters to improve indium bump to bump bonding

摘要

The plating characteristics of a commercially available indium plating solution are examined and optimized to help meet the increasing performance demands of integrated circuits requiring substantial numbers of electrical interconnections over large areas. Current fabrication techniques rely on evaporation of soft metals, such as indium, into lift-off resist profiles. This becomes increasingly difficult to accomplish as pitches decrease and aspect ratios increase. To minimize pixel dimensions and maximize the number of pixels per unit area, lithography and electrochemical deposition (ECD) of indium has been investigated. Pulse ECD offers the capability of improving large area uniformity ideal for large area device hybridization. Electrochemical experimentation into lithographically patterned molds allow for large areas of bumps to be fabricated for low temperature indium to indium bonds. The galvanic pulse profile, in conjunction with the bath configuration, determines the uniformity of the plated array. This pulse is manipulated to produce optimal properties for hybridizing arrays of aligned and bonded indium bumps. The physical properties of the indium bump arrays are examined using a white light interferometer, a SEM and tensile pull testing. This paper provides details from the electroplating processes as well as conclusions leading to optimized plating conditions.