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Conductance Modeling of High-A Al_2O_3 Gate Dielectrics Prepared by Oxidation of Aluminum Thin Films

机译:铝薄膜氧化制备高A Al_2O_3栅介质的电导模型

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摘要

High-quality thin layers of high-k gate dielectrics with high quality and performance, including low leakage current, has become a great challenge in order to increase the scale of integration of miniaturized components and circuits (1). To decrease the gate leakage current and increase the gate capacitance, high dielectric constant materials have been studied to replace the conventional silicon oxinitride (SiO_xN_y) as gate dielectric (1,2). High gate capacitance means low equivalent oxide thickness (EOT) and allows better control of the electric charges in the channel regions as well as low gate leakage current reduces standby power dissipation (1,2).
机译:为了增加小型化元件和电路的集成规模,具有高品质和性能的高质量薄层高k栅极电介质(包括低漏电流)已成为一项巨大的挑战。为了降低栅极泄漏电流并增加栅极电容,已经研究了高介电常数的材料来代替常规的氧氮化硅(SiO_xN_y)作为栅极介电层(1,2)。高栅极电容意味着低等效氧化物厚度(EOT),并且可以更好地控制沟道区域中的电荷,而低栅极泄漏电流则可以降低待机功耗(1,2)。

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  • 会议地点 Sao Paulo(BR);Sao Paulo(BR)
  • 作者单位

    University of Sao Paulo, LSI/PSI/EPUSP Av. Prof. Luciano Gualberto, 158, trav.3, Sao Paulo, SP, CEP 05508-900, Brasil;

    University of Sao Paulo, LSI/PSI/EPUSP Av. Prof. Luciano Gualberto, 158, trav.3, Sao Paulo, SP, CEP 05508-900, Brasil;

    University of Sao Paulo, LSI/PSI/EPUSP Av. Prof. Luciano Gualberto, 158, trav.3, Sao Paulo, SP, CEP 05508-900, Brasil rnFaculdade de Tecnologia de Sao Paulo - FATEC/SP/CEETEPS Av. Tiradentes, 615 - CEP 01101-010 Sao Paulo, Brazil;

    University of Sao Paulo, LSI/PSI/EPUSP Av. Prof. Luciano Gualberto, 158, trav.3, Sao Paulo, SP, CEP 05508-900, Brasil;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 半导体技术;
  • 关键词

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