A Novel Approach for Reversible Realization of 4 × 4 Bit Vedic Multiplier Circuit

摘要

The availability of fast and efficient processing systems is the basic requirement of current era. In digital systems, multiplications is one of the major operations, which limit the speed and efficiency of the system. This paper describes a novel approach for the Reversible realization of 4-Bit Vedic multiplier circuit with optimized performance parameters. Vedic multipliers are based on the concept of Vedic mathematics. It is a very fast multiplier, as it generates all the partial products and their sum in single step only. Moreover, designing of this multiplier using reversible approach will lead to the low loss fast multiplier circuits for digital systems. Some parameters indicating performance of the circuit, such as number of gates (TG), constant inputs (CI), garbage outputs (GO) and quantum cost (QC) of proposed multiplier design is also compared and analyzed with the earlier designs.