Future Challenges and Diversifications for Nanoelectronics by the End of the Roadmap and Beyond

摘要

The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power, high performance and increased functionalities. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to reduce power consumption and manage low supply voltage. Muftigate architectures increase MOSFETs driyabihty, reduce power, and allow new memory devices opportunities for future applications. By introducing new materials(HiK, Ge, III-V, Carbon based materials like diamond, graphene and CNTs, molecules,...), and new functions such as sensing and actuation allowing to interface the outside world (M/NEMS, filters, Imagers,...), Si based CMOS will be scaled beyond the ITRS as the System-on-ChipAVafer Platform. The Heterogeneous integration of these devices with CMOS will require new 3D and Packaging schemes leading to the increase of effective packing density, improving systems figures of merit.