Process window-based feature and die failure rate prediction

摘要

Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been usedto quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is ofmost interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, orinterlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal andvia, or unwanted bridging of patterns between layers.We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturingdistribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure ratefor all features within the die is known, then by extension the failure rate for the entire die can be known. Sinceestimating the process window exhaustively for all in-die locations is not possible, we first identify process windowlimiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for bothsystematic failure of an individual feature instance as well as stochastic failure for repeating patterns.