Design of Multiplier and Accumulator Unit for Low Power Applications

摘要

In recent growing of portable and multimedia devices, such as notebooks, and video phones, motivated the researchers to design low power VLSI circuits. Multiplier Accumulator Unit (MAC) is a major element of DSP. The speed of systems is based on the speed of MAC unit. This paper demonstrates the hardware-efficient MAC module with the help of using Vedic multiplier. This paper compares the proposed MAC module designs with the conventional MAC unit utilizing Vedic multiplier. The proposed scheme shows good performance in terms of low power dissipation MAC unit and analyzed using Tanner EDA tool.