A 40nm 7Gb/s/pin Single-ended Transceiver with Jitter and ISI Reduction Techniques for High-Speed DRAM Interface

摘要

A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40nm DRAM process. DRAM optimized LC I'LL achieves inductor Q of 3.86 and results in random jitter of 670fs rim. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap, hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to the integrating DFE. Moreover, on-chip de-emphasis circuit in TX multiplexer reduces 151 of both on and off chip.