Vertical Si p-MOS transistor selectively grown by low pressure chemical vapour deposition

摘要

Low pressure chemical vapour deposition was used to define the channel length of verticla Si p-MOS transistors. Comparing to a conventional laterla transistor, the vertical structure is expected to enhance the packing dneisyt. The growth technique permits an easy reduction of the channel length without complex technological preparation steps. Besides, it allows a selective deposition in which facet grwoth occurs, which in turn leads to a thinner channel length compared to the distance between the two pn-junctions in the volume area. Therefore, the facet growth leads to a shift of the punch-through effect to higher voltages. Device characteristics of a non-optimized transistor geometry, on which the gate oxide is prepared after the epitaxial growth, with a channel length of approximately 250 nm and a gate oxide thiciness of 12 nm, show a transconductance of 70 mS mm~-1, anideal sub-threshold behaviour of 100 mV dec~-1, an off-current below 10~-12 A mum~-2 and a breakthrough voltage |V_D|>4 V. Devices with a preparation of the gate oxide before epitaxial growth have also been studied. These ddevices show a transconductance of 25 mS mm~-1 for a gate oxide thickness of 40 nm.