Programmable Quasi Cyclic LDPC Encoder Architecture

摘要

To meet the requirements of future wideband wireless communications, a parameter-configurable encoder architecture is proposed in this paper for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) codes with high throughput. Distinguished from normal encoder, a CPU-liked architecture including an application specific instruction set and a specialized arithmetic logic unit (ALU) as well as a parity matrix RAM is proposed. The encoding algorithm has been classified into three basic operations. By defining three instructions, arbitrary QC-LDPC encoding can be implemented. The instruction RAM and parity matrix RAM can be configured by external bus to support different sizes and rates. Compared with other pure logical circuit architectures, the CPU-like architecture achieves 1 Gbps throughput reconfigurable LDPC encoding with smaller circuit.