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Nonuniform sampling digital PLL with fast error correction technique

机译:具有快速纠错技术的非均匀采样数字PLL

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摘要

A non-uniform sampling Time Delay Digital Tanlock Loop with an enhanced frequency acquisition performance is proposed in this work. An error detection circuitry is utilized to adjust the loop gain before the system goes out of the locking range. The process is controlled by a finite state machine. Through this adaptive process, the system can efficiently overcome frequency disturbances that may cause the loop to go out of lock. The performance of the proposed system under noise free conditions has been investigated by analysis and computer simulation. It is shown that the new developed loop can offer rapid acquisition and good tracking performance over a wide locking range.
机译:在这项工作中提出了一种具有增强频率采集性能的非均匀采样时间延迟数字Tanlock循环。 错误检测电路用于调节系统越过锁定范围之前的环路增益。 该过程由有限状态机控制。 通过这种自适应过程,系统可以有效地克服可能导致循环超出锁定的频率干扰。 通过分析和计算机仿真研究了在无噪声条件下的提出的系统的性能。 结果表明,新的发达环路可以在宽锁定范围内提供快速采集和良好的跟踪性能。

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